1. Field of the Invention
The present invention broadly relates to the electric connection of an electronic power device to its package.
In particular, but not limited to, the invention relates to a device which is fabricated with MOS technology to have at least one gate finger region and source regions on either sides of the gate region, the device also having at least one first-level metal layer arranged to independently contact said gate region and said source regions, and a protective passivation layer on top of the gate region.
The invention further relates to an advantageous method of electrically bonding the power device to its package. For convenience of explanation, the description below will make reference to discrete power components.
2. Description of the Related Art
As is well known, factors of prime importance in electronic power devices are minimized resistive contributions (Ron) and enhanced heat dissipation from the device when in its conduction mode.
At present, an assembly technique whereby the bonding wires are replaced with suitably shaped metal strips, or bridging strips, has met both requirements. This technique has proved itself in the instance of bipolar power devices. Also, European Patent No. 0179714 is evidence of a mixed bonding technique, whereby bonding wires are used along with bridging strips as shown in FIG. 1, being known since 1985.
Recently, an effort has been made to extend the mixed bonding technique to small packages, i.e., packages that enclose small-size integrated circuits, where contacting a pad with a clip would use up an unacceptably large amount of area. As an example, with a 7 mm2 device, contacting a gate termination by means of a clip would expend some 0.5 mm2, or 7%, of the active area. On the other hand, if a gate termination were contacted by means of a standard-gage bonding wire, the pad bulk would be brought down five times or less, i.e., to occupy less than 1% of the active area.
For a small-size package, or micro-package, the advantages brought about by the above mixed technique are as tabulated here below:
Resistive ContributionsDevice-to-Distribution ofThermalAssemblyPackageCurrent acrossResistance toTechniqueConnectionDevice SurfaceHeat DissipationStandard  2 mΩ1.5 mΩ10° C./WBridge0.5 mΩ0.1 mΩ 7° C./WGain1.5 mΩ(75%)1.4 mΩ(93%) 3° C./W (30%)
However, this mixed bonding technique is subject to certain constraints when used with MOS devices, due to the presence of considerable fingered gate and source metal lines on the device front.
Bonding fingered structures by means of bridges currently involves breaking the wettable metal line short of the gate fingers, e.g., as shown schematically in FIG. 2.
FIG. 2 is reproduced from U.S. Pat. No. 6,040,626, which is incorporated by reference herein in its entirety, to show a vertical cross-section taken through a gate finger. The following layers are recognizable: gate metal (19a), source metal (18), passivation (27), wettable metal (25), conductive adhesive (46), and bridge (30) layers. The lack of wettable metal in the gate finger structure results, especially in structures that are considerable fingered, in a substantial loss of contact area that reflects significantly on the device output resistance (Ron).
In view of most of the applications on demand today favoring devices with a very low Ron and high speed for high frequency operation, avoidance of conflicting fingered structure requirements and resistive contributions is of primary concern.